;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 2.7.0 #4818 (May 31 2007)
; This file generated Mon Apr 30 18:24:05 2012
;--------------------------------------------------------
	.module rf
	.optsdcc -mmcs51 --model-large
	
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _rf_tx_enable
	.globl _rf_command
	.globl _IRCON2_P2IF
	.globl _IRCON2_UTX0IF
	.globl _IRCON2_UTX1IF
	.globl _IRCON2_P1IF
	.globl _IRCON2_WDTIF
	.globl _CY
	.globl _AC
	.globl _F0
	.globl _RS1
	.globl _RS0
	.globl _OV
	.globl _F1
	.globl _P
	.globl _IRCON_DMAIF
	.globl _IRCON_T1IF
	.globl _IRCON_T2IF
	.globl _IRCON_T3IF
	.globl _IRCON_T4IF
	.globl _IRCON_P0IF
	.globl _IRCON_STIF
	.globl _IEN1_DMAIE
	.globl _IEN1_T1IE
	.globl _IEN1_T2IE
	.globl _IEN1_T3IE
	.globl _IEN1_T4IE
	.globl _IEN1_P0IE
	.globl _IEN0_RFERRIE
	.globl _IEN0_ADCIE
	.globl _IEN0_URX0IE
	.globl _IEN0_URX1IE
	.globl _IEN0_ENCIE
	.globl _IEN0_STIE
	.globl _IEN0_EA
	.globl _EA
	.globl _P2_4
	.globl _P2_3
	.globl _P2_2
	.globl _P2_1
	.globl _P2_0
	.globl _S0CON_ENCIF_0
	.globl _S0CON_ENCIF_1
	.globl _P1_7
	.globl _P1_6
	.globl _P1_5
	.globl _P1_4
	.globl _P1_3
	.globl _P1_2
	.globl _P1_1
	.globl _P1_0
	.globl _TCON_IT0
	.globl _TCON_RFERRIF
	.globl _TCON_IT1
	.globl _TCON_URX0IF
	.globl _TCON_ADCIF
	.globl _TCON_URX1IF
	.globl _P0_0
	.globl _P0_1
	.globl _P0_2
	.globl _P0_3
	.globl _P0_4
	.globl _P0_5
	.globl _P0_6
	.globl _P0_7
	.globl _P2DIR
	.globl _P1DIR
	.globl _P0DIR
	.globl _U1GCR
	.globl _U1UCR
	.globl _U1BAUD
	.globl _U1BUF
	.globl _U1CSR
	.globl _P2INP
	.globl _P1INP
	.globl _P2SEL
	.globl _P1SEL
	.globl _P0SEL
	.globl _ADCCFG
	.globl _PERCFG
	.globl _B
	.globl _T4CC1
	.globl _T4CCTL1
	.globl _T4CC0
	.globl _T4CCTL0
	.globl _T4CTL
	.globl _T4CNT
	.globl _RFIF
	.globl _IRCON2
	.globl _T1CCTL2
	.globl _T1CCTL1
	.globl _T1CCTL0
	.globl _T1CTL
	.globl _T1CNTH
	.globl _T1CNTL
	.globl _RFST
	.globl _ACC
	.globl _T1CC2H
	.globl _T1CC2L
	.globl _T1CC1H
	.globl _T1CC1L
	.globl _T1CC0H
	.globl _T1CC0L
	.globl _RFD
	.globl _TIMIF
	.globl _DMAREQ
	.globl _DMAARM
	.globl _DMA0CFGH
	.globl _DMA0CFGL
	.globl _DMA1CFGH
	.globl _DMA1CFGL
	.globl _DMAIRQ
	.globl _PSW
	.globl _T3CC1
	.globl _T3CCTL1
	.globl _T3CC0
	.globl _T3CCTL0
	.globl _T3CTL
	.globl _T3CNT
	.globl _WDCTL
	.globl _T2CON
	.globl _MEMCTR
	.globl _CLKCON
	.globl _U0GCR
	.globl _U0UCR
	.globl _T2CNF
	.globl _U0BAUD
	.globl _U0BUF
	.globl _IRCON
	.globl _SLEEP
	.globl _RNDH
	.globl _RNDL
	.globl _ADCH
	.globl _ADCL
	.globl _IP1
	.globl _IEN1
	.globl _RCCTL
	.globl _ADCCON3
	.globl _ADCCON2
	.globl _ADCCON1
	.globl _ENCCS
	.globl _ENCDO
	.globl _ENCDI
	.globl _FWDATA
	.globl _FCTL
	.globl _FADDRH
	.globl _FADDRL
	.globl _FWT
	.globl _IP0
	.globl _IEN0
	.globl _IE
	.globl _T2THD
	.globl _T2TLD
	.globl _T2CAPHPH
	.globl _T2CAPLPL
	.globl _T2OF2
	.globl _T2OF1
	.globl _T2OF0
	.globl _P2
	.globl _T2PEROF2
	.globl _T2PEROF1
	.globl _T2PEROF0
	.globl _S1CON
	.globl _IEN2
	.globl _HSRC
	.globl _S0CON
	.globl _ST2
	.globl _ST1
	.globl _ST0
	.globl _T2CMP
	.globl __XPAGE
	.globl _DPS
	.globl _RFIM
	.globl _P1
	.globl _P0INP
	.globl _P1IEN
	.globl _PICTL
	.globl _P2IFG
	.globl _P1IFG
	.globl _P0IFG
	.globl _TCON
	.globl _PCON
	.globl _U0CSR
	.globl _DPH1
	.globl _DPL1
	.globl _DPH0
	.globl _DPL0
	.globl _SP
	.globl _P0
	.globl _rf_initialized
	.globl _rf_lock
	.globl _ft_buffer
	.globl _rf_mac_address
	.globl _rf_manfid
	.globl _tx_flags
	.globl _rx_flags
	.globl _rf_tx_power
	.globl _RFD_SHADOW
	.globl _RFSTATUS
	.globl _CHIPID
	.globl _CHVER
	.globl _FSMTC1
	.globl _RXFIFOCNT
	.globl _IOCFG3
	.globl _IOCFG2
	.globl _IOCFG1
	.globl _IOCFG0
	.globl _SHORTADDRL
	.globl _SHORTADDRH
	.globl _PANIDL
	.globl _PANIDH
	.globl _IEEE_ADDR7
	.globl _IEEE_ADDR6
	.globl _IEEE_ADDR5
	.globl _IEEE_ADDR4
	.globl _IEEE_ADDR3
	.globl _IEEE_ADDR2
	.globl _IEEE_ADDR1
	.globl _IEEE_ADDR0
	.globl _DACTSTL
	.globl _DACTSTH
	.globl _ADCTSTL
	.globl _ADCTSTH
	.globl _FSMSTATE
	.globl _AGCCTRLL
	.globl _AGCCTRLH
	.globl _MANORL
	.globl _MANORH
	.globl _MANANDL
	.globl _MANANDH
	.globl _FSMTCL
	.globl _FSMTCH
	.globl _RFPWR
	.globl _CSPT
	.globl _CSPCTRL
	.globl _CSPZ
	.globl _CSPY
	.globl _CSPX
	.globl _FSCTRLL
	.globl _FSCTRLH
	.globl _RXCTRL1L
	.globl _RXCTRL1H
	.globl _RXCTRL0L
	.globl _RXCTRL0H
	.globl _TXCTRLL
	.globl _TXCTRLH
	.globl _SYNCWORDL
	.globl _SYNCWORDH
	.globl _RSSIL
	.globl _RSSIH
	.globl _MDMCTRL1L
	.globl _MDMCTRL1H
	.globl _MDMCTRL0L
	.globl _MDMCTRL0H
	.globl _rf_channel_set
	.globl _rf_power_set
	.globl _rf_rx_enable
	.globl _rf_rx_disable
	.globl _rf_init
	.globl _rf_set_address
	.globl _rf_address_decoder_mode
	.globl _rf_analyze_rssi
	.globl _rf_cca_check
	.globl _rf_send_ack
	.globl _rf_write
	.globl _rf_mac_get
	.globl _rf_rx_callback
	.globl _rf_ISR
	.globl _rf_error_ISR
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
	.area RSEG    (DATA)
_P0	=	0x0080
_SP	=	0x0081
_DPL0	=	0x0082
_DPH0	=	0x0083
_DPL1	=	0x0084
_DPH1	=	0x0085
_U0CSR	=	0x0086
_PCON	=	0x0087
_TCON	=	0x0088
_P0IFG	=	0x0089
_P1IFG	=	0x008a
_P2IFG	=	0x008b
_PICTL	=	0x008c
_P1IEN	=	0x008d
_P0INP	=	0x008f
_P1	=	0x0090
_RFIM	=	0x0091
_DPS	=	0x0092
__XPAGE	=	0x0093
_T2CMP	=	0x0094
_ST0	=	0x0095
_ST1	=	0x0096
_ST2	=	0x0097
_S0CON	=	0x0098
_HSRC	=	0x0099
_IEN2	=	0x009a
_S1CON	=	0x009b
_T2PEROF0	=	0x009c
_T2PEROF1	=	0x009d
_T2PEROF2	=	0x009e
_P2	=	0x00a0
_T2OF0	=	0x00a1
_T2OF1	=	0x00a2
_T2OF2	=	0x00a3
_T2CAPLPL	=	0x00a4
_T2CAPHPH	=	0x00a5
_T2TLD	=	0x00a6
_T2THD	=	0x00a7
_IE	=	0x00a8
_IEN0	=	0x00a8
_IP0	=	0x00a9
_FWT	=	0x00ab
_FADDRL	=	0x00ac
_FADDRH	=	0x00ad
_FCTL	=	0x00ae
_FWDATA	=	0x00af
_ENCDI	=	0x00b1
_ENCDO	=	0x00b2
_ENCCS	=	0x00b3
_ADCCON1	=	0x00b4
_ADCCON2	=	0x00b5
_ADCCON3	=	0x00b6
_RCCTL	=	0x00b7
_IEN1	=	0x00b8
_IP1	=	0x00b9
_ADCL	=	0x00ba
_ADCH	=	0x00bb
_RNDL	=	0x00bc
_RNDH	=	0x00bd
_SLEEP	=	0x00be
_IRCON	=	0x00c0
_U0BUF	=	0x00c1
_U0BAUD	=	0x00c2
_T2CNF	=	0x00c3
_U0UCR	=	0x00c4
_U0GCR	=	0x00c5
_CLKCON	=	0x00c6
_MEMCTR	=	0x00c7
_T2CON	=	0x00c8
_WDCTL	=	0x00c9
_T3CNT	=	0x00ca
_T3CTL	=	0x00cb
_T3CCTL0	=	0x00cc
_T3CC0	=	0x00cd
_T3CCTL1	=	0x00ce
_T3CC1	=	0x00cf
_PSW	=	0x00d0
_DMAIRQ	=	0x00d1
_DMA1CFGL	=	0x00d2
_DMA1CFGH	=	0x00d3
_DMA0CFGL	=	0x00d4
_DMA0CFGH	=	0x00d5
_DMAARM	=	0x00d6
_DMAREQ	=	0x00d7
_TIMIF	=	0x00d8
_RFD	=	0x00d9
_T1CC0L	=	0x00da
_T1CC0H	=	0x00db
_T1CC1L	=	0x00dc
_T1CC1H	=	0x00dd
_T1CC2L	=	0x00de
_T1CC2H	=	0x00df
_ACC	=	0x00e0
_RFST	=	0x00e1
_T1CNTL	=	0x00e2
_T1CNTH	=	0x00e3
_T1CTL	=	0x00e4
_T1CCTL0	=	0x00e5
_T1CCTL1	=	0x00e6
_T1CCTL2	=	0x00e7
_IRCON2	=	0x00e8
_RFIF	=	0x00e9
_T4CNT	=	0x00ea
_T4CTL	=	0x00eb
_T4CCTL0	=	0x00ec
_T4CC0	=	0x00ed
_T4CCTL1	=	0x00ee
_T4CC1	=	0x00ef
_B	=	0x00f0
_PERCFG	=	0x00f1
_ADCCFG	=	0x00f2
_P0SEL	=	0x00f3
_P1SEL	=	0x00f4
_P2SEL	=	0x00f5
_P1INP	=	0x00f6
_P2INP	=	0x00f7
_U1CSR	=	0x00f8
_U1BUF	=	0x00f9
_U1BAUD	=	0x00fa
_U1UCR	=	0x00fb
_U1GCR	=	0x00fc
_P0DIR	=	0x00fd
_P1DIR	=	0x00fe
_P2DIR	=	0x00ff
;--------------------------------------------------------
; special function bits
;--------------------------------------------------------
	.area RSEG    (DATA)
_P0_7	=	0x0087
_P0_6	=	0x0086
_P0_5	=	0x0085
_P0_4	=	0x0084
_P0_3	=	0x0083
_P0_2	=	0x0082
_P0_1	=	0x0081
_P0_0	=	0x0080
_TCON_URX1IF	=	0x008f
_TCON_ADCIF	=	0x008d
_TCON_URX0IF	=	0x008b
_TCON_IT1	=	0x008a
_TCON_RFERRIF	=	0x0089
_TCON_IT0	=	0x0088
_P1_0	=	0x0090
_P1_1	=	0x0091
_P1_2	=	0x0092
_P1_3	=	0x0093
_P1_4	=	0x0094
_P1_5	=	0x0095
_P1_6	=	0x0096
_P1_7	=	0x0097
_S0CON_ENCIF_1	=	0x0099
_S0CON_ENCIF_0	=	0x0098
_P2_0	=	0x00a0
_P2_1	=	0x00a1
_P2_2	=	0x00a2
_P2_3	=	0x00a3
_P2_4	=	0x00a4
_EA	=	0x00af
_IEN0_EA	=	0x00af
_IEN0_STIE	=	0x00ad
_IEN0_ENCIE	=	0x00ac
_IEN0_URX1IE	=	0x00ab
_IEN0_URX0IE	=	0x00aa
_IEN0_ADCIE	=	0x00a9
_IEN0_RFERRIE	=	0x00a8
_IEN1_P0IE	=	0x00bd
_IEN1_T4IE	=	0x00bc
_IEN1_T3IE	=	0x00bb
_IEN1_T2IE	=	0x00ba
_IEN1_T1IE	=	0x00b9
_IEN1_DMAIE	=	0x00b8
_IRCON_STIF	=	0x00c7
_IRCON_P0IF	=	0x00c5
_IRCON_T4IF	=	0x00c4
_IRCON_T3IF	=	0x00c3
_IRCON_T2IF	=	0x00c2
_IRCON_T1IF	=	0x00c1
_IRCON_DMAIF	=	0x00c0
_P	=	0x00d0
_F1	=	0x00d1
_OV	=	0x00d2
_RS0	=	0x00d3
_RS1	=	0x00d4
_F0	=	0x00d5
_AC	=	0x00d6
_CY	=	0x00d7
_IRCON2_WDTIF	=	0x00ec
_IRCON2_P1IF	=	0x00eb
_IRCON2_UTX1IF	=	0x00ea
_IRCON2_UTX0IF	=	0x00e9
_IRCON2_P2IF	=	0x00e8
;--------------------------------------------------------
; overlayable register banks
;--------------------------------------------------------
	.area REG_BANK_0	(REL,OVR,DATA)
	.ds 8
;--------------------------------------------------------
; overlayable bit register bank
;--------------------------------------------------------
	.area BIT_BANK	(REL,OVR,DATA)
bits:
	.ds 1
	b0 = bits[0]
	b1 = bits[1]
	b2 = bits[2]
	b3 = bits[3]
	b4 = bits[4]
	b5 = bits[5]
	b6 = bits[6]
	b7 = bits[7]
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
;--------------------------------------------------------
; overlayable items in internal ram 
;--------------------------------------------------------
	.area OSEG    (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
	.area ISEG    (DATA)
;--------------------------------------------------------
; absolute internal ram data
;--------------------------------------------------------
	.area IABS    (ABS,DATA)
	.area IABS    (ABS,DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
	.area BSEG    (BIT)
;--------------------------------------------------------
; paged external ram data
;--------------------------------------------------------
	.area PSEG    (PAG,XDATA)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
	.area XSEG    (XDATA)
_MDMCTRL0H	=	0xdf02
_MDMCTRL0L	=	0xdf03
_MDMCTRL1H	=	0xdf04
_MDMCTRL1L	=	0xdf05
_RSSIH	=	0xdf06
_RSSIL	=	0xdf07
_SYNCWORDH	=	0xdf08
_SYNCWORDL	=	0xdf09
_TXCTRLH	=	0xdf0a
_TXCTRLL	=	0xdf0b
_RXCTRL0H	=	0xdf0c
_RXCTRL0L	=	0xdf0d
_RXCTRL1H	=	0xdf0e
_RXCTRL1L	=	0xdf0f
_FSCTRLH	=	0xdf10
_FSCTRLL	=	0xdf11
_CSPX	=	0xdf12
_CSPY	=	0xdf13
_CSPZ	=	0xdf14
_CSPCTRL	=	0xdf15
_CSPT	=	0xdf16
_RFPWR	=	0xdf17
_FSMTCH	=	0xdf20
_FSMTCL	=	0xdf21
_MANANDH	=	0xdf22
_MANANDL	=	0xdf23
_MANORH	=	0xdf24
_MANORL	=	0xdf25
_AGCCTRLH	=	0xdf26
_AGCCTRLL	=	0xdf27
_FSMSTATE	=	0xdf39
_ADCTSTH	=	0xdf3a
_ADCTSTL	=	0xdf3b
_DACTSTH	=	0xdf3c
_DACTSTL	=	0xdf3d
_IEEE_ADDR0	=	0xdf43
_IEEE_ADDR1	=	0xdf44
_IEEE_ADDR2	=	0xdf45
_IEEE_ADDR3	=	0xdf46
_IEEE_ADDR4	=	0xdf47
_IEEE_ADDR5	=	0xdf48
_IEEE_ADDR6	=	0xdf49
_IEEE_ADDR7	=	0xdf4a
_PANIDH	=	0xdf4b
_PANIDL	=	0xdf4c
_SHORTADDRH	=	0xdf4d
_SHORTADDRL	=	0xdf4e
_IOCFG0	=	0xdf4f
_IOCFG1	=	0xdf50
_IOCFG2	=	0xdf51
_IOCFG3	=	0xdf52
_RXFIFOCNT	=	0xdf53
_FSMTC1	=	0xdf54
_CHVER	=	0xdf60
_CHIPID	=	0xdf61
_RFSTATUS	=	0xdf62
_RFD_SHADOW	=	0xdfd9
_rf_tx_power::
	.ds 1
_rx_flags::
	.ds 1
_tx_flags::
	.ds 1
_rf_manfid::
	.ds 2
_rf_mac_address::
	.ds 13
_ft_buffer::
	.ds 8
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
	.area XABS    (ABS,XDATA)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
_rf_lock::
	.ds 3
_rf_initialized::
	.ds 1
	.area HOME    (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT1 (CODE)
	.area GSINIT2 (CODE)
	.area GSINIT3 (CODE)
	.area GSINIT4 (CODE)
	.area GSINIT5 (CODE)
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME    (CODE)
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area HOME    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_command'
;------------------------------------------------------------
;command                   Allocated to registers r2 
;fifo_count                Allocated to registers r3 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:117: void rf_command(uint8_t command)
;	-----------------------------------------
;	 function rf_command
;	-----------------------------------------
_rf_command:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
	mov	r2,dpl
;	../../Platform/nano/rf.c:119: if (command >= 0xE0)
	cjne	r2,#0xE0,00126$
00126$:
	jc	00115$
;	../../Platform/nano/rf.c:122: switch (command)
	cjne	r2,#0xE2,00128$
	sjmp	00103$
00128$:
	cjne	r2,#0xE3,00129$
	sjmp	00103$
00129$:
	cjne	r2,#0xE5,00106$
;	../../Platform/nano/rf.c:126: case ISTXON:
00103$:
;	../../Platform/nano/rf.c:127: fifo_count = RXFIFOCNT;
	mov	dptr,#_RXFIFOCNT
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
;	../../Platform/nano/rf.c:128: RFST = command;
	mov	_RFST,r2
;	../../Platform/nano/rf.c:129: pause_us(1);
	mov	dptr,#0x0001
	push	ar3
	lcall	_pause_us
	pop	ar3
;	../../Platform/nano/rf.c:130: if (fifo_count != RXFIFOCNT)
	mov	dptr,#_RXFIFOCNT
	movx	a,@dptr
	mov	r4,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	r6,#0x00
	mov	a,r3
	cjne	a,ar4,00132$
	mov	a,r6
	cjne	a,ar5,00132$
	ret
00132$:
;	../../Platform/nano/rf.c:132: RFST = ISFLUSHRX;
	mov	_RFST,#0xE6
;	../../Platform/nano/rf.c:133: RFST = ISFLUSHRX;
	mov	_RFST,#0xE6
;	../../Platform/nano/rf.c:135: break;
;	../../Platform/nano/rf.c:137: default:
	ret
00106$:
;	../../Platform/nano/rf.c:138: RFST = command;
	mov	_RFST,r2
;	../../Platform/nano/rf.c:139: }
	ret
00115$:
;	../../Platform/nano/rf.c:141: else if (command == SSTART)
	cjne	r2,#0xDE,00112$
;	../../Platform/nano/rf.c:143: RFIF &= ~IRQ_CSP_STOP;	/*clear IRQ flag*/
	anl	_RFIF,#0xFD
;	../../Platform/nano/rf.c:144: RFST = SSTOP;	/*make sure there is a stop in the end*/
	mov	_RFST,#0xDF
;	../../Platform/nano/rf.c:145: RFST = ISSTART;	/*start execution*/
	mov	_RFST,#0xFE
;	../../Platform/nano/rf.c:146: while((RFIF & IRQ_CSP_STOP) == 0);
00108$:
	mov	a,_RFIF
	jb	acc.1,00117$
	sjmp	00108$
00112$:
;	../../Platform/nano/rf.c:150: RFST = command;	/*write command*/
	mov	_RFST,r2
00117$:
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_channel_set'
;------------------------------------------------------------
;channel                   Allocated to registers r2 
;freq                      Allocated to registers r3 r4 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:166: portCHAR rf_channel_set(uint8_t channel)
;	-----------------------------------------
;	 function rf_channel_set
;	-----------------------------------------
_rf_channel_set:
	mov	r2,dpl
;	../../Platform/nano/rf.c:170: if ( (channel < 11) || (channel > 26) ) return -1;
	cjne	r2,#0x0B,00107$
00107$:
	jc	00101$
	mov	a,r2
	add	a,#0xff - 0x1A
	jnc	00102$
00101$:
	mov	dpl,#0xFF
	ret
00102$:
;	../../Platform/nano/rf.c:173: freq = (uint16_t) channel - 11;
	mov	ar3,r2
	mov	r4,#0x00
	mov	a,r3
	add	a,#0xf5
	mov	r3,a
	mov	a,r4
	addc	a,#0xff
	mov	r4,a
;	../../Platform/nano/rf.c:174: freq *= 5;	/*channel spacing*/
	push	ar2
	push	ar3
	push	ar4
	mov	dptr,#0x0005
	lcall	__mulint
	mov	r5,dpl
	mov	r6,dph
	dec	sp
	dec	sp
	pop	ar2
	mov	ar3,r5
	mov	ar4,r6
;	../../Platform/nano/rf.c:175: freq += 357; /*correct channel range*/
	mov	a,#0x65
	add	a,r3
	mov	r3,a
	mov	a,#0x01
	addc	a,r4
	mov	r4,a
;	../../Platform/nano/rf.c:176: freq |= 0x4000; /*LOCK_THR = 1*/
	orl	ar4,#0x40
;	../../Platform/nano/rf.c:178: FSCTRLH = (freq >> 8);
	mov	ar5,r4
	mov	r6,#0x00
	mov	dptr,#_FSCTRLH
	mov	a,r5
	movx	@dptr,a
	inc	dptr
	mov	a,r6
	movx	@dptr,a
;	../../Platform/nano/rf.c:179: FSCTRLL = (uint8_t)freq;	
	mov	dptr,#_FSCTRLL
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:181: return (int8_t) channel;
	mov	dpl,r2
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_power_set'
;------------------------------------------------------------
;new_power                 Allocated to registers r2 
;power                     Allocated to registers r3 r4 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:202: portCHAR rf_power_set(uint8_t new_power)
;	-----------------------------------------
;	 function rf_power_set
;	-----------------------------------------
_rf_power_set:
;	../../Platform/nano/rf.c:206: if (new_power > 100) return -1;
	mov	a,dpl
	mov	r2,a
	add	a,#0xff - 0x64
	jnc	00102$
	mov	dpl,#0xFF
	ret
00102$:
;	../../Platform/nano/rf.c:208: power = 31 * new_power;
	mov	a,r2
	mov	b,#0x1F
	mul	ab
	mov	r3,a
	mov	r4,b
;	../../Platform/nano/rf.c:209: power /= 100;
	push	ar2
	mov	a,#0x64
	push	acc
	clr	a
	push	acc
	mov	dpl,r3
	mov	dph,r4
	lcall	__divuint
	mov	r5,dpl
	mov	r6,dph
	dec	sp
	dec	sp
	pop	ar2
	mov	ar3,r5
	mov	ar4,r6
;	../../Platform/nano/rf.c:210: power += 0xA160;
	mov	a,#0x60
	add	a,r3
	mov	r3,a
	mov	a,#0xA1
	addc	a,r4
	mov	r4,a
;	../../Platform/nano/rf.c:213: TXCTRLH = (power >> 8);
	mov	ar5,r4
	mov	r6,#0x00
	mov	dptr,#_TXCTRLH
	mov	a,r5
	movx	@dptr,a
	inc	dptr
	mov	a,r6
	movx	@dptr,a
;	../../Platform/nano/rf.c:214: TXCTRLL = (uint8_t)power;	
	mov	dptr,#_TXCTRLL
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:216: rf_tx_power = (int8_t) new_power;
	mov	dptr,#_rf_tx_power
	mov	a,r2
	movx	@dptr,a
;	../../Platform/nano/rf.c:217: return rf_tx_power;
	mov	dpl,r2
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_rx_enable'
;------------------------------------------------------------
;------------------------------------------------------------
;	../../Platform/nano/rf.c:227: portCHAR rf_rx_enable(void)
;	-----------------------------------------
;	 function rf_rx_enable
;	-----------------------------------------
_rf_rx_enable:
;	../../Platform/nano/rf.c:229: if (rx_flags == 0)
	mov	dptr,#_rx_flags
	movx	a,@dptr
	mov	r2,a
	jnz	00108$
;	../../Platform/nano/rf.c:231: RFIF &= ~(IRQ_SFD);
	anl	_RFIF,#0xEF
;	../../Platform/nano/rf.c:233: IOCFG0 = 0x04;   // Set the FIFOP threshold
	mov	dptr,#_IOCFG0
	mov	a,#0x04
	movx	@dptr,a
	clr	a
	inc	dptr
	movx	@dptr,a
;	../../Platform/nano/rf.c:234: tx_flags = 0;
	mov	dptr,#_tx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:235: rx_flags = RX_ACTIVE;
	mov	dptr,#_rx_flags
	mov	a,#0x80
	movx	@dptr,a
;	../../Platform/nano/rf.c:236: S1CON &= ~(RFIF_0 | RFIF_1);
	anl	_S1CON,#0xFC
;	../../Platform/nano/rf.c:237: RFPWR &= ~RREG_RADIO_PD;	/*make sure it's powered*/
	mov	dptr,#_RFPWR
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_RFPWR
	mov	a,#0xF7
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:238: while((RFIF & IRQ_RREG_ON) == 0);	/*wait for power up*/
00101$:
	mov	a,_RFIF
	jnb	acc.7,00101$
;	../../Platform/nano/rf.c:239: SLEEP &= ~OSC_PD; /*Osc on*/
	anl	_SLEEP,#0xFB
;	../../Platform/nano/rf.c:240: while((SLEEP & XOSC_STB) == 0);	/*wait for power up*/
00104$:
	mov	a,_SLEEP
	jnb	acc.6,00104$
;	../../Platform/nano/rf.c:242: RFIM |= IRQ_SFD;
	orl	_RFIM,#0x10
;	../../Platform/nano/rf.c:243: RFIF &= ~(IRQ_SFD);
	anl	_RFIF,#0xEF
;	../../Platform/nano/rf.c:245: S1CON &= ~(RFIF_0 | RFIF_1);
	anl	_S1CON,#0xFC
;	../../Platform/nano/rf.c:246: IEN2 |= RFIE;
	orl	_IEN2,#0x01
;	../../Platform/nano/rf.c:247: rf_command(ISRXON);
	mov	dpl,#0xE2
	lcall	_rf_command
00108$:
;	../../Platform/nano/rf.c:250: return pdTRUE;
	mov	dpl,#0x01
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_rx_disable'
;------------------------------------------------------------
;------------------------------------------------------------
;	../../Platform/nano/rf.c:260: portCHAR rf_rx_disable(void)
;	-----------------------------------------
;	 function rf_rx_disable
;	-----------------------------------------
_rf_rx_disable:
;	../../Platform/nano/rf.c:262: RFIM &= ~IRQ_SFD;
	anl	_RFIM,#0xEF
;	../../Platform/nano/rf.c:264: rf_command(ISSTOP);
	mov	dpl,#0xFF
	lcall	_rf_command
;	../../Platform/nano/rf.c:265: rf_command(ISRFOFF);
	mov	dpl,#0xE5
	lcall	_rf_command
;	../../Platform/nano/rf.c:267: RFPWR |= RREG_RADIO_PD;		/*RF powerdown*/
	mov	dptr,#_RFPWR
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_RFPWR
	mov	a,#0x08
	orl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:268: IEN2 &= ~RFIE;
	anl	_IEN2,#0xFE
;	../../Platform/nano/rf.c:269: rx_flags = 0;
	mov	dptr,#_rx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:271: return pdTRUE;
	mov	dpl,#0x01
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_tx_enable'
;------------------------------------------------------------
;------------------------------------------------------------
;	../../Platform/nano/rf.c:281: portCHAR rf_tx_enable(void)
;	-----------------------------------------
;	 function rf_tx_enable
;	-----------------------------------------
_rf_tx_enable:
;	../../Platform/nano/rf.c:283: RFIM &= ~IRQ_SFD;
	anl	_RFIM,#0xEF
;	../../Platform/nano/rf.c:285: IEN2 &= ~RFIE;
	anl	_IEN2,#0xFE
;	../../Platform/nano/rf.c:286: tx_flags |= RX_ACTIVE;
	mov	dptr,#_tx_flags
	movx	a,@dptr
	orl	a,#0x80
	movx	@dptr,a
;	../../Platform/nano/rf.c:287: rx_flags = 0;
	mov	dptr,#_rx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:288: return pdTRUE;
	mov	dpl,#0x01
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_init'
;------------------------------------------------------------
;retval                    Allocated to registers 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:299: portCHAR rf_init(void)
;	-----------------------------------------
;	 function rf_init
;	-----------------------------------------
_rf_init:
;	../../Platform/nano/rf.c:303: if (rf_initialized) return pdTRUE;
	mov	dptr,#_rf_initialized
	movx	a,@dptr
	mov	r2,a
	jz	00102$
	mov	dpl,#0x01
	ret
00102$:
;	../../Platform/nano/rf.c:305: RFPWR &= ~RREG_RADIO_PD;	/*make sure it's powered*/
	mov	dptr,#_RFPWR
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_RFPWR
	mov	a,#0xF7
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:306: while ((RFPWR & ADI_RADIO_PD) == 1);
00103$:
	mov	dptr,#_RFPWR
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	anl	ar2,#0x10
	mov	r3,#0x00
	cjne	r2,#0x01,00130$
	cjne	r3,#0x00,00130$
	sjmp	00103$
00130$:
;	../../Platform/nano/rf.c:307: while((RFIF & IRQ_RREG_ON) == 0);	/*wait for power up*/
00106$:
	mov	a,_RFIF
	jnb	acc.7,00106$
;	../../Platform/nano/rf.c:308: SLEEP &= ~OSC_PD; /*Osc on*/
	anl	_SLEEP,#0xFB
;	../../Platform/nano/rf.c:309: while((SLEEP & XOSC_STB) == 0);	/*wait for power up*/
00109$:
	mov	a,_SLEEP
	jnb	acc.6,00109$
;	../../Platform/nano/rf.c:311: rx_flags = tx_flags = 0;
	mov	dptr,#_tx_flags
	clr	a
	movx	@dptr,a
	mov	dptr,#_rx_flags
	movx	@dptr,a
;	../../Platform/nano/rf.c:315: FSMTC1 &= ~ABORTRX_ON_SRXON;	/*don't abort reception, if enable called*/
	mov	dptr,#_FSMTC1
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_FSMTC1
	mov	a,#0xDF
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:316: MDMCTRL0H &= ~0x18;	 /* Generic client */
	mov	dptr,#_MDMCTRL0H
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0H
	mov	a,#0xE7
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:317: MDMCTRL0L &= ~0x10;	 /* no automatic ACK */
	mov	dptr,#_MDMCTRL0L
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0L
	mov	a,#0xEF
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:320: MDMCTRL1H = 0x14;	/* CC2420 behaviour*/
	mov	dptr,#_MDMCTRL1H
	mov	a,#0x14
	movx	@dptr,a
	clr	a
	inc	dptr
	movx	@dptr,a
;	../../Platform/nano/rf.c:321: MDMCTRL1L = 0x00;
	mov	dptr,#_MDMCTRL1L
	clr	a
	movx	@dptr,a
	inc	dptr
	movx	@dptr,a
;	../../Platform/nano/rf.c:326: rf_manfid = CHVER;
	mov	dptr,#_CHVER
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
;	../../Platform/nano/rf.c:327: rf_manfid <<= 8;		
	mov	ar3,r2
	mov	r2,#0x00
;	../../Platform/nano/rf.c:328: rf_manfid += CHIPID;
	mov	dptr,#_CHIPID
	movx	a,@dptr
	mov	r4,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	dptr,#_rf_manfid
	mov	a,r4
	add	a,r2
	movx	@dptr,a
	mov	a,r5
	addc	a,r3
	inc	dptr
	movx	@dptr,a
;	../../Platform/nano/rf.c:330: rf_channel_set(RF_DEFAULT_CHANNEL);
	mov	dpl,#0x16
	lcall	_rf_channel_set
;	../../Platform/nano/rf.c:333: rf_power_set(RF_DEFAULT_POWER);
	mov	dpl,#0x64
	lcall	_rf_power_set
;	../../Platform/nano/rf.c:343: rf_command(ISFLUSHTX);
	mov	dpl,#0xE7
	lcall	_rf_command
;	../../Platform/nano/rf.c:344: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
;	../../Platform/nano/rf.c:345: tx_flags = 0;
	mov	dptr,#_tx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:347: if( rf_lock == NULL )
	mov	dptr,#_rf_lock
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r4,a
	cjne	r2,#0x00,00117$
	cjne	r3,#0x00,00117$
	cjne	r4,#0x00,00117$
;	../../Platform/nano/rf.c:349: vSemaphoreCreateBinary( rf_lock );
	clr	a
	push	acc
	mov	dpl,#0x01
	lcall	_xQueueCreate
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	dec	sp
	mov	dptr,#_rf_lock
	mov	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	mov	a,r4
	movx	@dptr,a
	cjne	r2,#0x00,00135$
	cjne	r3,#0x00,00135$
	cjne	r4,#0x00,00135$
	sjmp	00113$
00135$:
	clr	a
	push	acc
	push	acc
	clr	a
	push	acc
	push	acc
	push	acc
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	_xQueueSend
	mov	a,sp
	add	a,#0xfb
	mov	sp,a
00113$:
;	../../Platform/nano/rf.c:351: if( rf_lock == NULL ) return pdFALSE;
	mov	dptr,#_rf_lock
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r4,a
	cjne	r2,#0x00,00117$
	cjne	r3,#0x00,00117$
	cjne	r4,#0x00,00117$
	mov	dpl,#0x00
	ret
00117$:
;	../../Platform/nano/rf.c:354: rf_rx_enable();
	lcall	_rf_rx_enable
;	../../Platform/nano/rf.c:356: rf_initialized = 1;
	mov	dptr,#_rf_initialized
	mov	a,#0x01
	movx	@dptr,a
;	../../Platform/nano/rf.c:357: return retval;
	mov	dpl,#0x01
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_set_address'
;------------------------------------------------------------
;address                   Allocated to stack - offset 1
;i                         Allocated to stack - offset 4
;ptr                       Allocated to registers 
;sloc0                     Allocated to stack - offset 5
;------------------------------------------------------------
;	../../Platform/nano/rf.c:365: void rf_set_address(sockaddr_t *address)
;	-----------------------------------------
;	 function rf_set_address
;	-----------------------------------------
_rf_set_address:
	push	_bp
	mov	_bp,sp
	push	dpl
	push	dph
	push	b
	inc	sp
	inc	sp
	inc	sp
;	../../Platform/nano/rf.c:370: switch(address->addr_type)
	mov	r0,_bp
	inc	r0
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	lcall	__gptrget
	mov	r5,a
	cjne	r5,#0x03,00116$
	ljmp	00102$
00116$:
	cjne	r5,#0x04,00117$
	sjmp	00118$
00117$:
	ljmp	00109$
00118$:
;	../../Platform/nano/rf.c:373: ptr = &IEEE_ADDR0;
;	../../Platform/nano/rf.c:374: for(i=0; i<8;i++)
	mov	r0,_bp
	inc	r0
	mov	a,#0x01
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	@r0,#_IEEE_ADDR0
	inc	r0
	mov	@r0,#(_IEEE_ADDR0 >> 8)
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	@r0,#0x00
00105$:
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	cjne	@r0,#0x08,00119$
00119$:
	jnc	00108$
;	../../Platform/nano/rf.c:376: *ptr++ = address->address[i];
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	a,@r0
	add	a,r5
	mov	r3,a
	clr	a
	addc	a,r6
	mov	r4,a
	mov	ar2,r7
	mov	dpl,r3
	mov	dph,r4
	mov	b,r2
	lcall	__gptrget
	mov	r3,a
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	mov	a,r3
	movx	@dptr,a
	inc	dptr
	dec	r0
	mov	@r0,dpl
	inc	r0
	mov	@r0,dph
;	../../Platform/nano/rf.c:374: for(i=0; i<8;i++)
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	inc	@r0
	sjmp	00105$
00108$:
;	../../Platform/nano/rf.c:378: PANIDH = address->address[8];
	mov	r0,_bp
	inc	r0
	mov	a,#0x01
	add	a,@r0
	mov	r2,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r3,a
	inc	r0
	mov	ar4,@r0
	mov	a,#0x08
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	__gptrget
	mov	r5,a
	mov	dptr,#_PANIDH
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:379: PANIDL = address->address[9];
	mov	a,#0x09
	add	a,r2
	mov	r2,a
	clr	a
	addc	a,r3
	mov	r3,a
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	mov	r2,a
	mov	dptr,#_PANIDL
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:380: break;
	ljmp	00109$
;	../../Platform/nano/rf.c:382: case ADDR_802_15_4_PAN_SHORT:
00102$:
;	../../Platform/nano/rf.c:383: SHORTADDRH = address->address[0];
	mov	r0,_bp
	inc	r0
	mov	a,#0x01
	add	a,@r0
	mov	r2,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r3,a
	inc	r0
	mov	ar4,@r0
	mov	ar5,r2
	mov	ar6,r3
	mov	ar7,r4
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	__gptrget
	mov	dptr,#_SHORTADDRH
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:384: SHORTADDRL = address->address[1];
	mov	a,#0x01
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	__gptrget
	mov	dptr,#_SHORTADDRL
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:385: PANIDH = address->address[2];
	mov	a,#0x02
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	__gptrget
	mov	r5,a
	mov	dptr,#_PANIDH
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:386: PANIDL = address->address[3];
	mov	a,#0x03
	add	a,r2
	mov	r2,a
	clr	a
	addc	a,r3
	mov	r3,a
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	mov	r2,a
	mov	dptr,#_PANIDL
	movx	@dptr,a
	inc	dptr
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:391: }			
00109$:
	mov	sp,_bp
	pop	_bp
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_address_decoder_mode'
;------------------------------------------------------------
;param                     Allocated to registers r2 
;retval                    Allocated to registers 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:468: portCHAR rf_address_decoder_mode(uint8_t param)
;	-----------------------------------------
;	 function rf_address_decoder_mode
;	-----------------------------------------
_rf_address_decoder_mode:
;	../../Platform/nano/rf.c:473: if(param)
	mov	a,dpl
	mov	r2,a
	jz	00102$
;	../../Platform/nano/rf.c:483: MDMCTRL0H |= 0x08;	 /*Address-decode on */
	mov	dptr,#_MDMCTRL0H
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0H
	mov	a,#0x08
	orl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:484: MDMCTRL0L |= 0x10;	 /*automatic ACK */ /* Enable receive beacon if address decoder is enabled */
	mov	dptr,#_MDMCTRL0L
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0L
	mov	a,#0x10
	orl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
	sjmp	00103$
00102$:
;	../../Platform/nano/rf.c:490: MDMCTRL0H &= ~0x18;	 /* Generic client */
	mov	dptr,#_MDMCTRL0H
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0H
	mov	a,#0xE7
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
;	../../Platform/nano/rf.c:491: MDMCTRL0L &= ~0x10;	 /* no automatic ACK */
	mov	dptr,#_MDMCTRL0L
	movx	a,@dptr
	mov	r2,a
	inc	dptr
	movx	a,@dptr
	mov	r3,a
	mov	dptr,#_MDMCTRL0L
	mov	a,#0xEF
	anl	a,r2
	movx	@dptr,a
	inc	dptr
	mov	a,r3
	movx	@dptr,a
00103$:
;	../../Platform/nano/rf.c:494: return retval; 
	mov	dpl,#0x01
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_analyze_rssi'
;------------------------------------------------------------
;counter                   Allocated to registers 
;i                         Allocated to registers r4 
;sum                       Allocated to registers r2 r3 
;retval                    Allocated to registers r2 
;temp                      Allocated to registers r5 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:505: int8_t rf_analyze_rssi(void)
;	-----------------------------------------
;	 function rf_analyze_rssi
;	-----------------------------------------
_rf_analyze_rssi:
;	../../Platform/nano/rf.c:508: int16_t sum=0;
	mov	r2,#0x00
	mov	r3,#0x00
;	../../Platform/nano/rf.c:511: rf_command(ISRXON);
	mov	dpl,#0xE2
	push	ar2
	push	ar3
	lcall	_rf_command
;	../../Platform/nano/rf.c:512: pause_us(16);				/* waiting one symbol period */
	mov	dptr,#0x0010
	lcall	_pause_us
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:514: for(i=0; i<8; i++)
	mov	r4,#0x08
00103$:
;	../../Platform/nano/rf.c:516: temp = (int8_t)RSSIL;
	mov	dptr,#_RSSIL
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
;	../../Platform/nano/rf.c:517: temp -= 45;
	mov	a,r5
	add	a,#0xd3
;	../../Platform/nano/rf.c:518: sum += (int16_t)temp;
	mov	r5,a
	rlc	a
	subb	a,acc
	mov	r6,a
	mov	a,r5
	add	a,r2
	mov	r2,a
	mov	a,r6
	addc	a,r3
	mov	r3,a
;	../../Platform/nano/rf.c:519: pause_us(16);				/* waiting one symbol period */
	mov	dptr,#0x0010
	push	ar2
	push	ar3
	push	ar4
	lcall	_pause_us
	pop	ar4
	pop	ar3
	pop	ar2
	djnz	r4,00103$
;	../../Platform/nano/rf.c:514: for(i=0; i<8; i++)
;	../../Platform/nano/rf.c:521: sum /=8;
	mov	a,#0x08
	push	acc
	clr	a
	push	acc
	mov	dpl,r2
	mov	dph,r3
	lcall	__divsint
	mov	r4,dpl
	mov	r5,dph
	dec	sp
	dec	sp
	mov	ar2,r4
	mov	ar3,r5
;	../../Platform/nano/rf.c:522: retval = (int8_t)sum;
;	../../Platform/nano/rf.c:524: return retval; 
	mov	dpl,r2
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_cca_check'
;------------------------------------------------------------
;slotted                   Allocated to stack - offset -3
;backoff_count             Allocated to registers 
;counter                   Allocated to registers r4 
;cca                       Allocated to registers r3 
;retval                    Allocated to registers r2 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:533: portCHAR rf_cca_check(uint8_t backoff_count, uint8_t slotted)
;	-----------------------------------------
;	 function rf_cca_check
;	-----------------------------------------
_rf_cca_check:
	push	_bp
	mov	_bp,sp
;	../../Platform/nano/rf.c:536: portCHAR retval = pdTRUE;
	mov	r2,#0x01
;	../../Platform/nano/rf.c:538: rf_command(ISRXON);
	mov	dpl,#0xE2
	push	ar2
	lcall	_rf_command
;	../../Platform/nano/rf.c:540: pause_us(16);
	mov	dptr,#0x0010
	lcall	_pause_us
;	../../Platform/nano/rf.c:541: pause_us(16);
	mov	dptr,#0x0010
	lcall	_pause_us
;	../../Platform/nano/rf.c:542: pause_us(16);
	mov	dptr,#0x0010
	lcall	_pause_us
;	../../Platform/nano/rf.c:543: pause_us(16);
	mov	dptr,#0x0010
	lcall	_pause_us
	pop	ar2
;	../../Platform/nano/rf.c:544: switch (slotted)
	mov	r0,_bp
	dec	r0
	dec	r0
	dec	r0
	cjne	@r0,#0x00,00127$
	sjmp	00112$
00127$:
	mov	r0,_bp
	dec	r0
	dec	r0
	dec	r0
	cjne	@r0,#0x01,00115$
;	../../Platform/nano/rf.c:548: if(RFSTATUS & CCA)
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r4,a
	mov	a,r3
	jnb	acc.0,00110$
;	../../Platform/nano/rf.c:551: cca=1;
	mov	r3,#0x01
;	../../Platform/nano/rf.c:552: while(cca!=0) 
	mov	r4,#0x00
00106$:
	cjne	r3,#0x00,00131$
	sjmp	00115$
00131$:
;	../../Platform/nano/rf.c:554: if(counter > 1)
	mov	a,r4
	add	a,#0xff - 0x01
	jnc	00103$
;	../../Platform/nano/rf.c:555: cca=0;
	mov	r3,#0x00
00103$:
;	../../Platform/nano/rf.c:556: pause_us(250);
	mov	dptr,#0x00FA
	push	ar2
	push	ar3
	push	ar4
	lcall	_pause_us
	pop	ar4
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:557: if(!(RFSTATUS & CCA))
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jb	acc.0,00105$
;	../../Platform/nano/rf.c:559: cca=0;
	mov	r3,#0x00
;	../../Platform/nano/rf.c:560: retval = pdFALSE;
	mov	r2,#0x00
00105$:
;	../../Platform/nano/rf.c:562: counter++;
	inc	r4
	sjmp	00106$
00110$:
;	../../Platform/nano/rf.c:566: retval = pdFALSE;
	mov	r2,#0x00
;	../../Platform/nano/rf.c:567: break;
;	../../Platform/nano/rf.c:569: case 0:
	sjmp	00115$
00112$:
;	../../Platform/nano/rf.c:570: if(!(RFSTATUS & CCA))
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r4,a
	mov	a,r3
	jb	acc.0,00115$
;	../../Platform/nano/rf.c:572: retval = pdFALSE;
	mov	r2,#0x00
;	../../Platform/nano/rf.c:578: }
00115$:
;	../../Platform/nano/rf.c:579: return retval;		
	mov	dpl,r2
	pop	_bp
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_send_ack'
;------------------------------------------------------------
;pending                   Allocated to registers r2 
;------------------------------------------------------------
;	../../Platform/nano/rf.c:588: void rf_send_ack(uint8_t pending)
;	-----------------------------------------
;	 function rf_send_ack
;	-----------------------------------------
_rf_send_ack:
;	../../Platform/nano/rf.c:590: if(pending)
	mov	a,dpl
	mov	r2,a
	jz	00102$
;	../../Platform/nano/rf.c:592: rf_command(ISACKPEND);
	mov	dpl,#0xE9
	ljmp	_rf_command
00102$:
;	../../Platform/nano/rf.c:596: rf_command(ISACK);
	mov	dpl,#0xE8
	ljmp	_rf_command
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_write'
;------------------------------------------------------------
;buffer                    Allocated to stack - offset 1
;counter                   Allocated to registers r3 
;i                         Allocated to registers r2 
;retval                    Allocated to stack - offset 4
;length                    Allocated to stack - offset 5
;ptr                       Allocated to stack - offset 7
;sloc0                     Allocated to stack - offset 10
;------------------------------------------------------------
;	../../Platform/nano/rf.c:616: portCHAR rf_write(buffer_t *buffer)
;	-----------------------------------------
;	 function rf_write
;	-----------------------------------------
_rf_write:
	push	_bp
	mov	_bp,sp
	push	dpl
	push	dph
	push	b
	mov	a,sp
	add	a,#0x0c
	mov	sp,a
;	../../Platform/nano/rf.c:619: portCHAR retval = pdTRUE;
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	@r0,#0x01
;	../../Platform/nano/rf.c:620: int16_t length =  buffer->buf_end - buffer->buf_ptr;
	mov	r0,_bp
	inc	r0
	mov	a,#0x22
	add	a,@r0
	mov	r6,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r7,a
	inc	r0
	mov	ar5,@r0
	mov	dpl,r6
	mov	dph,r7
	mov	b,r5
	lcall	__gptrget
	mov	r6,a
	inc	dptr
	lcall	__gptrget
	mov	r7,a
	mov	r0,_bp
	inc	r0
	mov	a,_bp
	add	a,#0x0a
	mov	r1,a
	mov	a,#0x20
	add	a,@r0
	mov	@r1,a
	clr	a
	inc	r0
	addc	a,@r0
	inc	r1
	mov	@r1,a
	inc	r0
	inc	r1
	mov	a,@r0
	mov	@r1,a
	mov	a,_bp
	add	a,#0x0a
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	lcall	__gptrget
	mov	r5,a
	inc	dptr
	lcall	__gptrget
	mov	r2,a
	mov	a,r6
	clr	c
	subb	a,r5
	mov	r6,a
	mov	a,r7
	subb	a,r2
	mov	r7,a
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	@r0,ar6
	inc	r0
	mov	@r0,ar7
;	../../Platform/nano/rf.c:623: if (rx_flags & RX_ACTIVE)
	mov	dptr,#_rx_flags
	movx	a,@dptr
	mov	r4,a
	jnb	acc.7,00107$
;	../../Platform/nano/rf.c:625: if ( (RFSTATUS & FIFOP) || (RFSTATUS & SFD) )
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r4,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	a,r4
	jb	acc.2,00103$
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r4,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	a,r4
	jnb	acc.1,00107$
00103$:
;	../../Platform/nano/rf.c:630: if ((RFSTATUS & FIFOP))
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r4,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	a,r4
	jnb	acc.2,00102$
;	../../Platform/nano/rf.c:632: rf_command(ISFLUSHTX);
	mov	dpl,#0xE7
	lcall	_rf_command
;	../../Platform/nano/rf.c:633: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
;	../../Platform/nano/rf.c:634: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
00102$:
;	../../Platform/nano/rf.c:637: retval = pdFALSE;		
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	@r0,#0x00
00107$:
;	../../Platform/nano/rf.c:641: rf_tx_enable();
	lcall	_rf_tx_enable
;	../../Platform/nano/rf.c:642: if ( (length <= 128) && (retval == pdTRUE) )
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	clr	c
	mov	a,#0x80
	subb	a,@r0
	mov	a,#(0x00 ^ 0x80)
	inc	r0
	mov	b,@r0
	xrl	b,#0x80
	subb	a,b
	clr	a
	rlc	a
	mov	r4,a
	jz	00162$
	ljmp	00126$
00162$:
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	cjne	@r0,#0x01,00163$
	sjmp	00164$
00163$:
	ljmp	00126$
00164$:
;	../../Platform/nano/rf.c:644: uint8_t *ptr = buffer->buf + buffer->buf_ptr;
	push	ar4
	mov	r0,_bp
	inc	r0
	mov	a,#0x2C
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	a,_bp
	add	a,#0x0a
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	lcall	__gptrget
	mov	r4,a
	inc	dptr
	lcall	__gptrget
	mov	r2,a
	mov	a,r4
	add	a,r5
	mov	r5,a
	mov	a,r2
	addc	a,r6
	mov	r6,a
	mov	a,_bp
	add	a,#0x07
	mov	r0,a
	mov	@r0,ar5
	inc	r0
	mov	@r0,ar6
	inc	r0
	mov	@r0,ar7
;	../../Platform/nano/rf.c:646: rf_command(ISFLUSHTX);
	mov	dpl,#0xE7
	push	ar4
	lcall	_rf_command
	pop	ar4
;	../../Platform/nano/rf.c:648: RFD = (length+2);
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	ar2,@r0
	mov	a,#0x02
	add	a,r2
	mov	_RFD,a
;	../../Platform/nano/rf.c:710: return retval;		
	pop	ar4
;	../../Platform/nano/rf.c:650: for (i = 0 ; i < length ; i++)
	mov	a,_bp
	add	a,#0x07
	mov	r0,a
	mov	ar2,@r0
	inc	r0
	mov	ar3,@r0
	inc	r0
	mov	ar5,@r0
	mov	r6,#0x00
00131$:
	push	ar4
	mov	ar7,r6
	mov	r4,#0x00
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	clr	c
	mov	a,r7
	subb	a,@r0
	mov	a,r4
	xrl	a,#0x80
	inc	r0
	mov	b,@r0
	xrl	b,#0x80
	subb	a,b
	clr	a
	rlc	a
	pop	ar4
	jz	00134$
;	../../Platform/nano/rf.c:652: RFD = *ptr++;
	mov	dpl,r2
	mov	dph,r3
	mov	b,r5
	lcall	__gptrget
	mov	_RFD,a
	inc	dptr
	mov	r2,dpl
	mov	r3,dph
;	../../Platform/nano/rf.c:650: for (i = 0 ; i < length ; i++)
	inc	r6
	sjmp	00131$
00134$:
;	../../Platform/nano/rf.c:654: RFD = (0);
	mov	_RFD,#0x00
;	../../Platform/nano/rf.c:655: RFD = (0);
	mov	_RFD,#0x00
;	../../Platform/nano/rf.c:657: if (rf_cca_check(0,0) == pdFALSE)
	push	ar4
	clr	a
	push	acc
	mov	dpl,#0x00
	lcall	_rf_cca_check
	mov	r2,dpl
	dec	sp
	pop	ar4
	mov	a,r2
	jnz	00109$
;	../../Platform/nano/rf.c:659: rf_command(ISFLUSHTX);
	mov	dpl,#0xE7
	lcall	_rf_command
;	../../Platform/nano/rf.c:660: rx_flags = 0;
	mov	dptr,#_rx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:661: rf_rx_enable();
	lcall	_rf_rx_enable
;	../../Platform/nano/rf.c:663: return pdTRUE+1;
	mov	dpl,#0x02
	ljmp	00135$
00109$:
;	../../Platform/nano/rf.c:666: i= 0;
	mov	r2,#0x00
;	../../Platform/nano/rf.c:667: RFIF &= ~IRQ_TXDONE;
	anl	_RFIF,#0xBF
;	../../Platform/nano/rf.c:668: while (i++ < 3)
00116$:
	mov	ar3,r2
	inc	r2
	cjne	r3,#0x03,00167$
00167$:
	jnc	00118$
;	../../Platform/nano/rf.c:670: rf_command(ISTXON);
	mov	dpl,#0xE3
	push	ar2
	push	ar4
	lcall	_rf_command
	pop	ar4
	pop	ar2
;	../../Platform/nano/rf.c:672: while(!(RFSTATUS & TX_ACTIVE) && (counter++ < 200))
	mov	r3,#0x00
00111$:
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jb	acc.4,00113$
	mov	ar5,r3
	inc	r3
	cjne	r5,#0xC8,00170$
00170$:
	jnc	00113$
;	../../Platform/nano/rf.c:674: pause_us(10);
	mov	dptr,#0x000A
	push	ar2
	push	ar3
	push	ar4
	lcall	_pause_us
	pop	ar4
	pop	ar3
	pop	ar2
	sjmp	00111$
00113$:
;	../../Platform/nano/rf.c:676: if (RFSTATUS & TX_ACTIVE) i = 200;
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r3,a
	inc	dptr
	movx	a,@dptr
	mov	r5,a
	mov	a,r3
	jnb	acc.4,00116$
	mov	r2,#0xC8
	sjmp	00116$
00118$:
;	../../Platform/nano/rf.c:679: if (i ==3)
	cjne	r2,#0x03,00119$
;	../../Platform/nano/rf.c:684: rf_command(ISRFOFF);
	mov	dpl,#0xE5
	push	ar4
	lcall	_rf_command
	pop	ar4
;	../../Platform/nano/rf.c:685: tx_flags = 0;
	mov	dptr,#_tx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:686: retval = pdFALSE;
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	@r0,#0x00
;	../../Platform/nano/rf.c:690: while(!(RFIF & IRQ_TXDONE))
	sjmp	00126$
00119$:
	mov	a,_RFIF
	jb	acc.6,00126$
;	../../Platform/nano/rf.c:692: pause_us(10);
	mov	dptr,#0x000A
	push	ar4
	lcall	_pause_us
	pop	ar4
	sjmp	00119$
00126$:
;	../../Platform/nano/rf.c:697: if ((retval == pdTRUE) && (length > 128))
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	cjne	@r0,#0x01,00129$
	mov	a,r4
	jz	00129$
;	../../Platform/nano/rf.c:704: retval = pdFALSE;
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	@r0,#0x00
00129$:
;	../../Platform/nano/rf.c:706: tx_flags = 0;
	mov	dptr,#_tx_flags
	clr	a
	movx	@dptr,a
;	../../Platform/nano/rf.c:707: rf_rx_enable();
	lcall	_rf_rx_enable
;	../../Platform/nano/rf.c:710: return retval;		
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	dpl,@r0
00135$:
	mov	sp,_bp
	pop	_bp
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_mac_get'
;------------------------------------------------------------
;address                   Allocated to registers r2 r3 r4 
;i                         Allocated to stack - offset 1
;sloc0                     Allocated to stack - offset 2
;------------------------------------------------------------
;	../../Platform/nano/rf.c:719: portCHAR rf_mac_get(sockaddr_t *address)
;	-----------------------------------------
;	 function rf_mac_get
;	-----------------------------------------
_rf_mac_get:
	push	_bp
	mov	a,sp
	mov	_bp,a
	add	a,#0x04
	mov	sp,a
;	../../Platform/nano/rf.c:721: mac_get(address);
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	push	ar2
	push	ar3
	push	ar4
	lcall	_mac_get
	pop	ar4
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:722: if (address->addr_type == ADDR_NONE)
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	jz	00116$
	ljmp	00104$
00116$:
;	../../Platform/nano/rf.c:725: flash_read(&ft_buffer[0], 0x1FFF8, 8);
	push	ar2
	push	ar3
	push	ar4
	mov	a,#0x08
	push	acc
	mov	a,#0xF8
	push	acc
	mov	a,#0xFF
	push	acc
	mov	a,#0x01
	push	acc
	clr	a
	push	acc
	mov	dptr,#_ft_buffer
	mov	b,#0x00
	lcall	_flash_read
	mov	a,sp
	add	a,#0xfb
	mov	sp,a
	pop	ar4
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:726: for (i=0; i<8; i++)
	mov	a,#0x01
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	mov	r0,_bp
	inc	r0
	mov	@r0,#0x00
00105$:
	mov	r0,_bp
	inc	r0
	cjne	@r0,#0x08,00117$
00117$:
	jnc	00108$
;	../../Platform/nano/rf.c:728: address->address[7-i] = ft_buffer[i];
	push	ar2
	push	ar3
	push	ar4
	mov	r0,_bp
	inc	r0
	mov	a,#0x07
	clr	c
	subb	a,@r0
	mov	r0,_bp
	inc	r0
	inc	r0
	add	a,r5
	mov	@r0,a
	clr	a
	addc	a,r6
	inc	r0
	mov	@r0,a
	inc	r0
	mov	@r0,ar7
	mov	r0,_bp
	inc	r0
	mov	a,@r0
	add	a,#_ft_buffer
	mov	dpl,a
	clr	a
	addc	a,#(_ft_buffer >> 8)
	mov	dph,a
	movx	a,@dptr
	mov	r4,a
	mov	r0,_bp
	inc	r0
	inc	r0
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	mov	a,r4
	lcall	__gptrput
;	../../Platform/nano/rf.c:726: for (i=0; i<8; i++)
	mov	r0,_bp
	inc	r0
	inc	@r0
	pop	ar4
	pop	ar3
	pop	ar2
	sjmp	00105$
00108$:
;	../../Platform/nano/rf.c:730: address->addr_type = ADDR_802_15_4_LONG;
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
;	../../Platform/nano/rf.c:731: if (stack_check_broadcast(address->address, ADDR_802_15_4_LONG) == pdTRUE)
	mov	a,#0x01
	lcall	__gptrput
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	push	ar2
	push	ar3
	push	ar4
	mov	a,#0x01
	push	acc
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	_stack_check_broadcast
	mov	r5,dpl
	dec	sp
	pop	ar4
	pop	ar3
	pop	ar2
	cjne	r5,#0x01,00119$
	sjmp	00120$
00119$:
	ljmp	00102$
00120$:
;	../../Platform/nano/rf.c:733: debug("No address in flash.\n");
	mov	dptr,#__str_0
	push	ar2
	push	ar3
	push	ar4
	lcall	_debug_constant
	pop	ar4
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:734: address->address[0]=0x00;
	mov	a,#0x01
	add	a,r2
	mov	r5,a
	clr	a
	addc	a,r3
	mov	r6,a
	mov	ar7,r4
	push	ar2
	push	ar3
	push	ar4
	mov	ar2,r5
	mov	ar3,r6
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:735: address->address[1]=0x00;
	mov	a,#0x01
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:736: address->address[2]=0x00;
	mov	a,#0x02
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:737: address->address[3]=0x00;
	mov	a,#0x03
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:738: address->address[4]=0x00;
	mov	a,#0x04
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:739: address->address[5]=0x00;
	mov	a,#0x05
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:745: address->address[6]= 0x12;
	mov	a,#0x06
	add	a,r5
	mov	r2,a
	clr	a
	addc	a,r6
	mov	r3,a
	mov	ar4,r7
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,#0x12
	lcall	__gptrput
;	../../Platform/nano/rf.c:746: address->address[7]= 0x34;
	mov	a,#0x07
	add	a,r5
	mov	r5,a
	clr	a
	addc	a,r6
	mov	r6,a
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	mov	a,#0x34
	lcall	__gptrput
;	../../Platform/nano/rf.c:752: return pdTRUE;
	pop	ar4
	pop	ar3
	pop	ar2
;	../../Platform/nano/rf.c:746: address->address[7]= 0x34;
00102$:
;	../../Platform/nano/rf.c:749: mac_set(address);
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	_mac_set
00104$:
;	../../Platform/nano/rf.c:752: return pdTRUE;
	mov	dpl,#0x01
	mov	sp,_bp
	pop	_bp
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_rx_callback'
;------------------------------------------------------------
;param                     Allocated to registers 
;b                         Allocated to stack - offset 1
;i                         Allocated to stack - offset 4
;ptr                       Allocated to registers r2 r3 r4 
;tmp_16                    Allocated to registers r5 r6 
;sloc0                     Allocated to stack - offset 5
;------------------------------------------------------------
;	../../Platform/nano/rf.c:757: void rf_rx_callback(void *param)
;	-----------------------------------------
;	 function rf_rx_callback
;	-----------------------------------------
_rf_rx_callback:
	push	_bp
	mov	a,sp
	mov	_bp,a
	add	a,#0x07
	mov	sp,a
;	../../Platform/nano/rf.c:766: b = stack_buffer_get(20);
	mov	dptr,#0x0014
	lcall	_stack_buffer_get
	mov	r2,dpl
	mov	r3,dph
	mov	r4,b
	mov	r0,_bp
	inc	r0
	mov	@r0,ar2
	inc	r0
	mov	@r0,ar3
	inc	r0
	mov	@r0,ar4
;	../../Platform/nano/rf.c:767: if (b)
	mov	r0,_bp
	inc	r0
	mov	a,@r0
	inc	r0
	orl	a,@r0
	inc	r0
	orl	a,@r0
	jnz	00144$
	ljmp	00126$
00144$:
;	../../Platform/nano/rf.c:769: b->options.type = BUFFER_DATA;
	mov	r0,_bp
	inc	r0
	mov	a,#0x26
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:775: b->to = MODULE_RF_802_15_4;
	mov	r0,_bp
	inc	r0
	mov	a,#0x1E
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	mov	a,#0x08
	lcall	__gptrput
;	../../Platform/nano/rf.c:777: b->dir = BUFFER_UP;
	mov	r0,_bp
	inc	r0
	mov	a,#0x1F
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:778: b->buf_ptr = 0;
	mov	r0,_bp
	inc	r0
	mov	a,#0x20
	add	a,@r0
	mov	r5,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r6,a
	inc	r0
	mov	ar7,@r0
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	clr	a
	lcall	__gptrput
	inc	dptr
	clr	a
	lcall	__gptrput
;	../../Platform/nano/rf.c:780: tmp_16 = 0;
	mov	r5,#0x00
	mov	r6,#0x00
;	../../Platform/nano/rf.c:781: if ((RFSTATUS & SFD) != 0)
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r7,a
	inc	dptr
	movx	a,@dptr
	anl	ar7,#0x02
	mov	r2,#0x00
	clr	a
	cjne	r7,#0x00,00145$
	cjne	r2,#0x00,00145$
	inc	a
00145$:
;	../../Platform/nano/rf.c:784: while( ((RFSTATUS & SFD) != 0) && (tmp_16++ > 1000))
	jnz	00106$
	mov	r3,a
	mov	r4,a
00102$:
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r7,a
	inc	dptr
	movx	a,@dptr
	anl	ar7,#0x02
	mov	r2,#0x00
	clr	a
	cjne	r7,#0x00,00148$
	cjne	r2,#0x00,00148$
	inc	a
00148$:
	jnz	00142$
	mov	ar7,r3
	mov	ar2,r4
	inc	r3
	cjne	r3,#0x00,00151$
	inc	r4
00151$:
	clr	c
	mov	a,#0xE8
	subb	a,r7
	mov	a,#0x03
	subb	a,r2
	jc	00102$
00142$:
	mov	ar5,r3
	mov	ar6,r4
00106$:
;	../../Platform/nano/rf.c:788: if (tmp_16 <= 1000)
	clr	c
	mov	a,#0xE8
	subb	a,r5
	mov	a,#0x03
	subb	a,r6
	jnc	00153$
	ljmp	00121$
00153$:
;	../../Platform/nano/rf.c:833: if( ((RFSTATUS & FIFOP)) && (! ((RFSTATUS & FIFO)) ) ) 
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jnb	acc.2,00117$
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jb	acc.3,00117$
;	../../Platform/nano/rf.c:839: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
;	../../Platform/nano/rf.c:840: rf_rx_enable();
	lcall	_rf_rx_enable
	ljmp	00122$
00117$:
;	../../Platform/nano/rf.c:842: else if( ((RFSTATUS & FIFO)) && (! ((RFSTATUS & SFD)) ))
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jb	acc.3,00156$
	ljmp	00122$
00156$:
	mov	dptr,#_RFSTATUS
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	mov	a,r5
	jnb	acc.1,00157$
	ljmp	00122$
00157$:
;	../../Platform/nano/rf.c:845: i = RFD & 0x7F;
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	a,#0x7F
	anl	a,_RFD
	mov	@r0,a
;	../../Platform/nano/rf.c:846: i -= 2;
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	dec	@r0
	dec	@r0
;	../../Platform/nano/rf.c:848: b->buf_end = i;
	mov	r0,_bp
	inc	r0
	mov	a,#0x22
	add	a,@r0
	mov	r6,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r7,a
	inc	r0
	mov	ar5,@r0
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	ar2,@r0
	mov	r3,#0x00
	mov	dpl,r6
	mov	dph,r7
	mov	b,r5
	mov	a,r2
	lcall	__gptrput
	inc	dptr
	mov	a,r3
	lcall	__gptrput
;	../../Platform/nano/rf.c:849: ptr = b->buf;
	mov	r0,_bp
	inc	r0
	mov	a,#0x2C
	add	a,@r0
	mov	r2,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r3,a
	inc	r0
	mov	ar4,@r0
;	../../Platform/nano/rf.c:851: while(i)
	mov	a,_bp
	add	a,#0x04
	mov	r0,a
	mov	ar5,@r0
00107$:
	mov	a,r5
	jz	00109$
;	../../Platform/nano/rf.c:853: *ptr++ = RFD;			
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,_RFD
	lcall	__gptrput
	inc	dptr
	mov	r2,dpl
	mov	r3,dph
;	../../Platform/nano/rf.c:854: i--;
	dec	r5
	sjmp	00107$
00109$:
;	../../Platform/nano/rf.c:857: b->options.rf_dbm = ((int8_t) RFD) - 45;
	mov	r0,_bp
	inc	r0
	mov	a,#0x26
	add	a,@r0
	mov	r2,a
	clr	a
	inc	r0
	addc	a,@r0
	mov	r3,a
	inc	r0
	mov	ar4,@r0
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	a,#0x01
	add	a,r2
	mov	@r0,a
	clr	a
	addc	a,r3
	inc	r0
	mov	@r0,a
	inc	r0
	mov	@r0,ar4
	mov	a,_RFD
	add	a,#0xd3
	mov	r5,a
	mov	a,_bp
	add	a,#0x05
	mov	r0,a
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	mov	a,r5
	lcall	__gptrput
;	../../Platform/nano/rf.c:858: b->options.rf_lqi = RFD;
	mov	a,#0x02
	add	a,r2
	mov	r2,a
	clr	a
	addc	a,r3
	mov	r3,a
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,_RFD
	lcall	__gptrput
;	../../Platform/nano/rf.c:860: if (b->options.rf_lqi & 0x80 || b->options.rf_lqi & 0x40)
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	mov	r5,a
	jb	acc.7,00110$
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	mov	r5,a
	jnb	acc.6,00111$
00110$:
;	../../Platform/nano/rf.c:862: b->options.rf_lqi &= ~0x80;
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	lcall	__gptrget
	mov	r5,a
	anl	ar5,#0x7F
	mov	dpl,r2
	mov	dph,r3
	mov	b,r4
	mov	a,r5
	lcall	__gptrput
;	../../Platform/nano/rf.c:863: stack_buffer_push(b);
	mov	r0,_bp
	inc	r0
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	lcall	_stack_buffer_push
;	../../Platform/nano/rf.c:864: b = 0;
	mov	r0,_bp
	inc	r0
	clr	a
	mov	@r0,a
	inc	r0
	mov	@r0,a
	inc	r0
	mov	@r0,a
00111$:
;	../../Platform/nano/rf.c:873: rf_rx_enable();
	lcall	_rf_rx_enable
	sjmp	00122$
00121$:
;	../../Platform/nano/rf.c:883: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
00122$:
;	../../Platform/nano/rf.c:885: if (b != 0) 
	mov	r0,_bp
	inc	r0
	cjne	@r0,#0x00,00161$
	inc	r0
	cjne	@r0,#0x00,00161$
	inc	r0
	cjne	@r0,#0x00,00161$
	sjmp	00128$
00161$:
;	../../Platform/nano/rf.c:888: stack_buffer_free(b);
	mov	r0,_bp
	inc	r0
	mov	dpl,@r0
	inc	r0
	mov	dph,@r0
	inc	r0
	mov	b,@r0
	lcall	_stack_buffer_free
	sjmp	00128$
00126$:
;	../../Platform/nano/rf.c:894: rf_command(ISFLUSHRX);
	mov	dpl,#0xE6
	lcall	_rf_command
00128$:
	mov	sp,_bp
	pop	_bp
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_ISR'
;------------------------------------------------------------
;prev_task                 Allocated to registers r2 
;event                     Allocated to stack - offset 1
;------------------------------------------------------------
;	../../Platform/nano/rf.c:907: void rf_ISR( void ) interrupt (RF_VECTOR)
;	-----------------------------------------
;	 function rf_ISR
;	-----------------------------------------
_rf_ISR:
	push	bits
	push	acc
	push	b
	push	dpl
	push	dph
	push	(0+2)
	push	(0+3)
	push	(0+4)
	push	(0+5)
	push	(0+6)
	push	(0+7)
	push	(0+0)
	push	(0+1)
	push	psw
	mov	psw,#0x00
	push	_bp
	mov	a,sp
	mov	_bp,a
	add	a,#0x05
	mov	sp,a
;	../../Platform/nano/rf.c:911: if ((RFIF & IRQ_SFD) && (tx_flags == 0))
	mov	a,_RFIF
	jnb	acc.4,00104$
	mov	dptr,#_tx_flags
	movx	a,@dptr
	mov	r2,a
	jnz	00104$
;	../../Platform/nano/rf.c:914: event.process = rf_rx_callback;
	mov	a,_bp
	inc	a
	mov	r0,a
	mov	@r0,#_rf_rx_callback
	inc	r0
	mov	@r0,#(_rf_rx_callback >> 8)
;	../../Platform/nano/rf.c:915: event.param = (void *) 0;
	mov	r2,_bp
	inc	r2
	mov	a,#0x02
	add	a,r2
	mov	r0,a
	mov	@r0,#0x00
	inc	r0
	mov	@r0,#0x00
	inc	r0
	mov	@r0,#0x00
;	../../Platform/nano/rf.c:917: prev_task = xQueueSendFromISR(events, &event, prev_task);
	mov	r3,#0x00
	mov	r4,#0x40
	mov	dptr,#_events
	movx	a,@dptr
	mov	r5,a
	inc	dptr
	movx	a,@dptr
	mov	r6,a
	inc	dptr
	movx	a,@dptr
	mov	r7,a
	clr	a
	push	acc
	push	ar2
	push	ar3
	push	ar4
	mov	dpl,r5
	mov	dph,r6
	mov	b,r7
	lcall	_xQueueSendFromISR
	mov	r2,dpl
	mov	a,sp
	add	a,#0xfc
	mov	sp,a
;	../../Platform/nano/rf.c:918: if (prev_task == pdTRUE)
	cjne	r2,#0x01,00104$
;	../../Platform/nano/rf.c:920: taskYIELD();
	lcall	_vPortYield
00104$:
;	../../Platform/nano/rf.c:923: if (RFIF & IRQ_SFD)
	mov	a,_RFIF
	jnb	acc.4,00107$
;	../../Platform/nano/rf.c:925: RFIF &= ~IRQ_SFD;
	anl	_RFIF,#0xEF
00107$:
;	../../Platform/nano/rf.c:928: S1CON &= ~(RFIF_0 | RFIF_1);
	anl	_S1CON,#0xFC
	mov	sp,_bp
	pop	_bp
	pop	psw
	pop	(0+1)
	pop	(0+0)
	pop	(0+7)
	pop	(0+6)
	pop	(0+5)
	pop	(0+4)
	pop	(0+3)
	pop	(0+2)
	pop	dph
	pop	dpl
	pop	b
	pop	acc
	pop	bits
	reti
;------------------------------------------------------------
;Allocation info for local variables in function 'rf_error_ISR'
;------------------------------------------------------------
;------------------------------------------------------------
;	../../Platform/nano/rf.c:939: void rf_error_ISR( void ) interrupt (RFERR_VECTOR)
;	-----------------------------------------
;	 function rf_error_ISR
;	-----------------------------------------
_rf_error_ISR:
;	../../Platform/nano/rf.c:941: TCON_RFERRIF = 0;
	clr	_TCON_RFERRIF
	reti
;	eliminated unneeded push/pop psw
;	eliminated unneeded push/pop dpl
;	eliminated unneeded push/pop dph
;	eliminated unneeded push/pop b
;	eliminated unneeded push/pop acc
	.area CSEG    (CODE)
	.area CONST   (CODE)
__str_0:
	.ascii "No address in flash."
	.db 0x0A
	.db 0x00
	.area XINIT   (CODE)
__xinit__rf_lock:
; generic printIvalPtr
	.byte #0x00,#0x00,#0x00
__xinit__rf_initialized:
	.db #0x00
	.area CABS    (ABS,CODE)
